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| W83194BR-740 STEPLESS CLOCK FOR SIS735/740 CHIPSET W83194BR-740 Data Sheet Revision History Pages 1 2 3 4 5 6 7 8 9 10 n.a. n.a. 02/Apr 1.0 Dates Version Version On Web n.a. 1.0 All of the versions before 0.50 are for internal use. Change version and version on web site to 1.0 Main Contents Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -1- Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 1. GENERAL DESCRIPTION The W83194BR-740 is a Clock Synthesizer for SiS 735/740 chipset. W83194BR-740 provides all clocks required for high-speed RISC or CISC microprocessor such as AMD K7, and also provides 16 different frequencies of CPU clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR-740 makes SDRAM in synchronous or asynchronous frequency with CPU clocks. The W83194BR-740 provides step-less frequency programming by controlling the VCO freq. and the programmable AGP, PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. Spread spectrum built in at 0.5% or 0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface The W83194BR-740 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2. PRODUCT FEATURES * * * * * * * * * * * * * * * Supports AMD CPU with I2C. 3 CPU clocks (one free-running CPU clock) 2 AGP clocks 1 SDRAM output clock for chipset 1 IOAPIC clock 6 PCI synchronous clocks. Optional single or mixed supply: (Others Vdd = 3.3V, VddLCPU=2.5V) Skew---CPU to CPU < 175ps, CPU to SDRAM < 250ps, PCI to PCI < 500ps, AGP to AGP < 175ps Smooth frequency switch with selections from 66 to 200mhz I2C 2-Wire serial interface and I2C read back 0.5%, 0.25%center type, 0~0.5% down type spread spectrum to reduce EMI Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) 48 MHz for USB 24 MHz for super I/O Packaged in 48-pin SSOP -2- Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 3. PIN CONFIGURATION VddR REF0^/&FS0 REF1^/&FS1 Vss Vssosc Xin Xout Vss PCICLK_F^/&FS2 PCICLK1^/&FS3 VddP PCICLK2^ PCICLK3^ Vss PCICLK4^ PCICLK5^ VddAGP AGPCLK0 AGPCLK1 VssAGP Vdd48 48MHz^ 24_48MHz#/&AGPSEL Vss VddAPIC IOAPIC Vss VddC $CPUCLK0T $CPUCLK0C Vss VddC $CPUCLK1T Vss Reserved RESET# VddSD SDRAM_out VssD PCI_STOP# CPU_STOP# PD# SDRAM_STOP# AGP_STOP# SDATA* SDCLK* Vss Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 *:pull-up 120K &:pull-down 120K ^:double strength #:input active low $:open drain ALL PCICLK outputs have X1.5~X2 drive strength 4. PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional OD - Open drain # - Active Low * - Internal 120k pull-up 4.1 Crystal I/O SYMBOL Xin Xout PIN 6 7 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 4.2 CPU, SDRAM, AGP, PCI Clock Outputs SYMBOL PIN I/O FUNCTION Publication Release Date:May. 2001 Revision 1.0 -3- W83194BR-740 IOAPIC $CPUCLK0T $CPUCLK0C $CPUCLK1T 47 44,43 OUT OD 40 OD SDRAM_out 35 OUT PCICLK_F^/ &FS2 9 I/O PCICLK1^/ &FS3 10 I/O PCICLK^ [ 2:5 ] RESET# 12,13,15,16 37 OUT OD AGPCLK0 AGPCLK1 18,19 OUT 16.7/33MHz APIC clock for CPU and Chipset, selected by I2C. True CPU clock output and Complementary CPU clock output, open drain output type. This pin will be stopped by CPU_STOP# Low skew (< 250ps) clock outputs for host CPU clock output for chipset, open drain output type. This pin will not be stopped by CPU_STOP# SDRAM clock output which have syn. or asyn. Frequencies as CPU clocks. The clock phase is the same as CPUCLK0T and CPUCLK1T. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Interanl 120K pull-down. PCICLK_F outputs have 1.5X drive strength. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Internal 120K pull-down PCICLK1 outputs have 1.5X drive strength. Low skew (< 250ps) PCI clock outputs. ALL PCICLK outputs have 1.5X drive strength. Open Drain output type, 4ms low active pulse, when Watch Dog time out the all clock output recover to hardware FS0~FS3 setting. Low skew (< 250ps) AGP clock outputs. 4.3 I2C Control Interface SYMBOL *SDATA *SDCLK PIN 28 27 I/O I/O IN 2 FUNCTION Serial data of I C 2-wire control interface Serial clock of I2C 2-wire control interface 4.4 Fixed Frequency Outputs SYMBOL REF0^/&FS0 PIN 2 I/O I/O FUNCTION 3.3V, 14.318MHz reference clock output. Internal 120k pull-down. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. This pin has 1.5X drive strength. 3.3V , 14.318MHz reference clock output. Internal 120k pull-down. This pin has 1.5X drive strength. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Latched input for &AGPSEL at initial power up for Publication Release Date:May. 2001 Revision 1.0 REF1^/&FS1 3 I/O 24_48MHz#/&AGPSEL 23 I/O -4- W83194BR-740 48MHz ^ 22 O H/W selecting the output frequency of AGP clocks. Internal 120K pull-down. 24MHz or 48MHz selected by I2C programming control bit (Byte7, bit4),and default be 24MHz 48MHz output for USB. This pin has 1.5X drive strength. 4.5 Power Management Pins SYMBOL AGP_STOP# SDRAM_STOP# PD# CPU_STOP# PCI_STOP# PIN 29 30 31 32 33 FUNCTION AGP clock stop control pin. SDRAM clock stop control pin. Power Down pin, if PD#=0, all clocks are stopped. CPU clock stop control pin. PCI clock stop control pin. 4.6 Power Pins SYMBOL VddR VddAPIC Vdd VddC VddAGP VddP VddSD Vdd48 Vss VCO FS[3:0] (MHz) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 399.6 400 498 399 399.6 400 400 399 336 372 414 300 399.6 498 PIN 1 48 25 41,45 FUNCTION Power supply for REF. 3.3V Power supply for IOAPIC,2.5V. Power supply for core logic. 3.3V Power supply for CPUCLK1T, CPUCLK0T, and CPUCLK0C, 2.5V. 17 Power supply for AGP outputs. 11 Power supply for PCI outputs. 36 Power supply for SDRAM and 48/24MHz outputs. 21 Power supply for 48/24MHz outputs. 4,5,8,14,20,26,46,39,42 Circuit Ground. VCO/ CPU:SDRAM:PCI 6 6 2 4 4 3 3 3 5 3 3 4 6 4 2 4 6 3 4 3 3 3 4 4 3 3 3 3 3 4 3 3 4 2 2 5 6 3 2 4 3 4 VCO/AGP AGPSEL=0 AGPSEL=1 5. FREQUENCY SELECTION BY HARDWARE TABLE CPU SDRAM PCI (MHz) (MHz) (MHz) 66.6 100 166 133 66.6 100 100 133 112 124 138 150 66.6 124.5 66.6 100 166 133 100 66.6 133 100 112 124 138 150 133 166 33.3 33.3 33.2 33.3 33.3 33.3 33.3 33.3 37.3 31 34.5 30 33.3 31.13 AGP AGPSEL=0 AGPSEL=1 6 6 8 6 6 6 6 6 5 6 6 5 6 8 8 8 10 8 8 8 8 8 6 8 8 6 8 10 -5- 66.6 66.6 62.5 66.6 66.6 66.6 66.6 66.6 67.2 62 69 60 66.6 62.5 50 50 50 50 50 50 50 50 56 46.5 51.8 50 50 50 Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 1110 1111 300 480 2 3 3 4 5 5 5 8 6 10 150 160 100 120 30 32 60 60 50 48 6. FUNCTION DESCRIPTION 6.1 2-WIRE I2C CONTROL INTERFACE The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194BR-740 initializes with default register settings, and then itptional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-tohigh transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller : Clock Address A(6:0) & R/W Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop Set R/W to 1 when read back the data sequence is as follows, [1101 0011] : Clock Address A(6:0) & R/W Ack Byte 0 Ack Byte 1 Ack Byte2, 3, 4... until Stop 6.2 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. 6.2.1 Register 4: CPU Frequency Select Register (default = 0) Bit 7 6 5 4 3 2 @PowerUp 0 0 0 0 0 0 Pin Description SEL3 (for frequency table selection by software via I2C) SEL2 (for frequency table selection by software via I2C) SEL1 (for frequency table selection by software via I2C) SEL0 (for frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit 1,2, 7:4 SEL4 (for frequency table selection by software via I2C) -6Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 1 0 0 0 - SEL5 (for frequency table selection by software via I2C) 0 = Running 1 = Tristate all outputs VCO/AGP AGPSEL=0 AGPSEL=1 Frequency table by I2C VCO SEL[5:0] (MHz) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 011100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 399.6 400 498 399 399.6 400 400 399 336 372 414 300 399.6 498 300 480 420 432 333.2 388 408 416 420 428 412 420 424 428 412 420 424 432 VCO/ CPU:SDRAM:PCI 6 6 2 4 4 3 3 3 5 3 3 4 6 4 2 4 6 3 4 3 3 3 4 4 3 3 3 3 3 2 6 4 2 3 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 2 3 3 3 4 4 4 3 3 3 3 3 3 6 6 4 4 4 4 4 4 VCO/ CPU:SDRAM:PCI -7Publication Release Date:May. 2001 Revision 1.0 4 4 5 2 4 5 5 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 CPU SDRAM PCI (MHz) (MHz) (MHz) 66.6 100 166 133 66.6 100 100 133 112 124 138 150 66.6 124.5 150 160 66.6 100 166 133 100 66.6 133 100 112 124 138 150 133 166 100 120 33.3 33.3 33.2 33.3 33.3 33.3 33.3 33.3 37.3 31 34.5 30 33.3 31.13 30 32 AGP AGPSEL=0 AGPSEL=1 6 6 8 6 6 6 6 6 5 6 6 5 6 8 5 8 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 8 8 10 8 8 8 8 8 6 8 8 6 8 10 6 10 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 66.6 66.6 62.5 66.6 66.6 66.6 66.6 66.6 67.2 62 69 60 66.6 62.5 60 60 70 72 55.53 64.67 68 69.33 70 71.33 68.67 70 70.67 71.33 68.67 70 70.67 72 50 50 50 50 50 50 50 50 56 46.5 51.8 50 50 50 50 48 52.5 54 41.65 48.5 51 52 52.5 53.5 51.5 52.5 53 53.5 51.5 52.5 53 54 70 105 35 72 108 36 83.3 111.07 27.77 97 129.33 32.33 102 136 34 104 138.67 34.67 105 140 35 107 142.67 35.67 103 68.67 34.33 105 70 35 106 106 35.33 107 107 35.67 103 103 34.33 105 105 35 106 106 35.33 108 108 36 CPU SDRAM PCI (MHz) (MHz) (MHz) VCO SEL[5:0] (MHz) VCO/AGP AGPSEL=0 AGPSEL=1 AGP AGPSEL=0 AGPSEL=1 W83194BR-740 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 111100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 390 405 408 417 420 426 429 435 390 405 414 426 411 417 423 426 390 396 408 411 414 426 432 438 450 459 468 489 498 525 534 549 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 130 135 136 139 140 142 143 145 130 135 138 142 137 139 141 142 130 132 136 137 138 142 144 146 150 153 156 163 166 175 178 183 130 135 136 139 140 142 143 145 130 135 138 142 137 139 141 142 32.5 33.75 34 34.75 35 35.5 35.75 36.25 26 27 27.6 28.4 27.4 27.8 28.2 28.4 65 67.5 68 69.5 70 71 71.5 72.5 65 67.5 69 71 68.5 69.5 70.5 71 65 49.5 51 51.38 51.75 53.25 54 54.75 56.25 57.38 58.5 61.13 62.25 65.63 66.75 68.63 48.75 50.63 51 52.13 52.5 53.25 53.63 54.38 48.75 50.63 51.75 53.25 51.38 52.13 52.88 53.25 48.75 39.6 40.8 41.1 41.4 42.6 43.2 43.8 45 45.9 46.8 48.9 49.8 52.5 53.4 54.9 97.5 32.5 99 33 102 34 102.75 34.25 103.5 34.5 106.5 35.5 108 36 109.5 36.5 112.5 30 114.75 30.6 117 31.2 122.25 32.6 124.5 33.2 131.25 35 133.5 35.6 137.25 36.6 6.2.2 Register 5 : CPU Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 @PowerUp 1 1 0 0 1 Pin 43 Description Reserved 0 = 0.5% down type spread 1= Center type spread. 0 = Normal 1 = Spread Spectrum enabled 0 = 0.25% Center type Spread Spectrum Modulation 1 = 0.5% Center type Spread Spectrum Modulation $CPUCLK0C (Active / Inactive) -8Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 2 1 0 1 1 1 44 40 - $CPUCLK0T (Active / Inactive) $CPUCLK1T (Active / Inactive) Reserved 6.2.3 Register 6: PCI Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 @PowerUp 1 1 1 1 1 1 1 1 Pin 19 18 16 15 13 12 10 9 Description AGPCLK1 (Active / Inactive) AGPCLK0 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK_F (Active / Inactive) Pin 23 22 47 3 2 Description 24_48MHz (Active / Inactive) 48MHz (Active / Inactive) IOAPIC(Active / Inactive) 1 = 24_48MHz(pin23) is 24MHz 0 = 24_48MHz(pin23) is 48Mhz 1 = IOAPIC(pin47) is the frequency of PCI/2 0 = IOAPIC(pin47) is the frequency of PCI Reserved REF1 (Active / Inactive) REF0 (Active / Inactive) 6.2.4 Register 7: Control Register (1 = Active, 0 = Inactive) 6.2.5 Register 8: Control Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp X X X X X 1 0 0 Pin 23 10 9 3 2 Description Latched AGPSEL# Latched FS3# Latched FS2# Latched FS1# Latched FS0# ACskew2 (AGP to CPU skew program bit) ACskew1 (AGP to CPU skew program bit) ACskew0 (AGP to CPU skew program bit) 6.2.6 Register 9: Control Register(1 = Active, 0 = Inactive) Bit 7 6 5 4 3 @PowerUp 1 1 1 X X Pin Description Reserved 1 = $CPUCLK1T can be stopped by CPU_STOP# 0 = $CPUCLK1T free running Reserved Latched AGP_STOP# Latched CPU_STOP# -9Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 2 1 0 X X X - Latched PCI_STOP# Latched SDR_STOP# Latched PD# 6.2.7 Register 10: Watchdog Timer Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 X 0 0 0 0 0 0 Pin Enable Count Description 1 = start timer 0 = stop timer Second timeout status (READ ONLY) Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count 0 6.2.8 Register 11: M/N Program Register and Divisor Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 0 0 0 0 0 Pin Description N value bit 8 Test 1 (Internal test use) Test 0 (Internal test use) M value bit 4 M value bit 3 M value bit 2 M value bit 1 M value bit 0 6.2.9 Register 12: M/N Program Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description N value bit 7 N value bit 6 N value bit 5 N value bit 4 N value bit 3 N value bit 2 N value bit 1 N value bit 0 6.2.10 Register 13: Spread spectrum control Register Bit 7 6 5 4 3 @PowerUp 0 0 0 0 0 Pin Description Spread spectrum up count 3 Spread spectrum up count 2 Spread spectrum up count 1 Spread spectrum up count 0 Spread spectrum down count 3 - 10 Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 2 1 0 0 0 0 - Spread spectrum down count 2 Spread spectrum down count 1 Spread spectrum down count 0 6.2.11 Register 14: Divisor Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M Ratio SSEL3 (See CPU:SDRAM:PCI ratio selection table) Ratio SSEL2 (See CPU:SDRAM:PCI ratio selection table) Ratio SSEL1 (See CPU:SDRAM:PCI ratio selection table) Ratio SSEL0 (See CPU:SDRAM:PCI ratio selection table) AGP Ratio ASEL2 (See AGP ratio selection table) AGP Ratio ASEL1 (See AGP ratio selection table) AGP Ratio ASEL0 (See AGP ratio selection table) 6.2.12 Register 15: Winbond Chip ID Register (Read Only) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 1 0 0 0 1 0 Pin Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID 6.2.13 Register 16: Winbond Chip ID Register (Read Only) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 1 0 0 0 1 0 Pin Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Version ID Version ID Version ID Version ID - 11 - Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 1.CPU:SDRAM:PCI ratio selection table VCO/ SSEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CPU 2 2 3 3 3 3 3 4 4 4 4 6 6 6 6 6 VCO/ SDRAM 2 3 3 3 3 4 4 3 3 4 6 3 4 6 6 6 CPU/ PCI 5 5 3 4 5 4 5 3 4 3 3 2 2 2 3 4 2.AGP ratio selection table ASEL[2:0] 000 001 010 011 100 101 110 111 VCO/AGP 3 5 6 8 4 10 - 12 - Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 7. ORDERING INFORMATION Part Number W83194BR-740 Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C 8. HOW TO READ THE TOP MARKING W83194BR-740 28051234 942GED 1st line: Winbond logo and the type number: W83194BR-740 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 942 G E D 942: packages made in '99, week 42 G: assembly house ID; O means OSE, G means GR E: Internal use code D: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 13 - Publication Release Date:May. 2001 Revision 1.0 W83194BR-740 9. PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2727 North First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products Publication Release Date:May. 2001 Revision 1.0 - 14 - W83194BR-740 for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 15 - Publication Release Date:May. 2001 Revision 1.0 |
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